1. Field of the Invention
The present invention relates to an image device and a method of fabricating the same, and more particularly, to an image device having an opening in which an external connection electrode is formed and a method of fabricating the image device.
2. Description of the Related Art
Image devices refer to devices that convert optical signals to electric signals. For example, a charge coupled device (CCD) and a complementary metal-oxide semiconductor (CMOS) image sensor (CIS) are considered image devices. The CCD includes multiple MOS capacitors, which are operated by moving electric charges (carriers) produced by light. The CIS is driven by a CMOS circuit that controls multiple unit pixels and corresponding output signals. The CCD has a complicated driving method, large power consumption and a complicated fabricating process. Also, because a signal processing circuit cannot be integrated with a chip of the CCD, it is difficult to make a CCD in a single chip. In contrast, because CMOS image devices can be fabricated through previously used CMOS technology, research and development have focused on CMOS image devices that can be more easily fabricated. Examples of CMOS image devices will be described below.
FIGS. 1 through 3 are cross-sectional views of conventional image devices. Referring to FIG. 1, an image device includes a semiconductor substrate 1, metal interconnection patterns 2a, 2b and 2c stacked on the substrate 1 and an interlayer dielectric layer 3. A planarization layer and a color filter portion 8 are formed on the interlayer dielectric layer 3, which is schematically illustrated. The substrate 1 includes a photodiode (not shown) for receiving light L, e.g., from a photographing operation. When light L is incident on the photodiode, the interlayer dielectric layer 3 and the metal interconnection patterns 2a, 2b and 2c may interrupt the incidence of the light L. Thus, sensitivity is degraded due to the metal interconnection patterns, particularly as the size of a pixel in a CMOS image device is scaled down.
FIG. 2 is a cross-sectional view of an image device having a backside illumination structure. Referring to FIG. 2, the image device includes stacked metal interconnection patterns 2a, 2b and 2c, an interlayer dielectric layer 3, and a substrate 1 formed thereon. A support substrate 4 may be formed beneath a bottom surface of the interlayer dielectric layer 3 as necessary. The substrate 1 includes a photodiode (not shown) for receiving light L, e.g., from a photographing operation. When light L is incident on the photodiode, the interlayer dielectric layer 3 and the metal interconnection patterns 2a, 2b and 2c do not interrupt the incidence of the light L. In other words, the image device of FIG. 2 addresses the problem of the image device of FIG. 1 since the light L is incident on a backside 1′ of the substrate 1.
FIG. 3 is a cross-sectional view showing an external connection region of a backside-illumination-type image device having a backside 1a′. The conventional backside-illumination-type image device is divided into an active pixel region A, in which data received from a photodiode are processed; a logic circuit region B, positioned adjacent to the active pixel region A, in which signals received from the active pixel region A are converted to logic signals; and an external connection region C, positioned adjacent to the logic circuit region B, which outputs logic signals received from the logic circuit region B. An interlayer dielectric layer 3 and stacked metal interconnection patterns 2a, 2b and 2c are formed in each of the active pixel region A and logic circuit region B. The metal interconnection patterns may be formed as multiple layers, e.g., three layers including first, second and third metal interconnection patterns 2a, 2b and 2c. 
In the external connection region C, an external connection electrode 7 is formed within an opening 6. Because the external connection electrode 7 is simultaneously formed with the first metal interconnection pattern 2a, the opening 6 is formed by passing through a substrate la and extending into a portion of the interlayer dielectric layer 3. As a result, a step difference H occurs between the interlayer dielectric layers of the active pixel region A and the logic circuit region B, and the interlayer dielectric layer of the external connection region C. Therefore, when a material of the substrate la is different from that of the interlayer dielectric layer 3 (e.g., silicon and oxide), the opening 6 is formed by double etching. Also, when the external connection electrode 7 is simultaneously formed with the first metal interconnection pattern 2a, the thickness of the external connection electrode 7 is the same as that of the interconnection pattern 2a, and thus cannot be independently determined.